In the prior art it is well known that latching comparators comparing two input voltages have many applications such as analog to digital converters used in VCR. Such comparator includes a pair of differential inputs for receiving two input voltages to be compared, a pair of transistors differentially driven by the differential input voltages, and a pair of differential outputs. In such differentially operating latching comparators, even when the input voltage difference is zero the differential output voltage undesirably does not become zero, that is, there exists a nonzero input offset voltage which must be applied to drive the output voltage difference to zero. This offset voltage is unwanted because it leads to malfunction or wrong outputs as explained later in more detail. Especially the offset error is serious in latching comparators applied to A/D converter, because the comparators must respond at high speed to small signal inputs. Therefore reducing the offset voltage is desired in many applications.
The predominant source of the offset error is the mismatch of the transistor pair mainly due to a wafer process inaccuracy such as gate length variation, gate width variation, oxide thickness variation, etc. Accordingly, it is possible to reduce the offset voltage by using a large geometric size which makes it easier to match the transistor pair. However, the large geometry causes slow response and requires very wide area on the silicon resulting in the die cost increasing.